Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Analog-to-digital converters (ADC) may be used in digital serial input/output (I/O) receivers of various backplanes and/or interconnects. Examples of such digital serial I/O backplane/interconnect may include those implemented in accordance with Peripheral Component Interconnect Express (PCIe), version 3.0, published by PCI Special Interest Group (PCI-SIG) in November 2010, or Universal Serial Bus (USB), version 3.0, published by USB Implementers Forum (USB-IF) in November 2008, etc.
Many conventional ADCs used today are not all digital I/O based ADCs. A type of ADC that may be commonly used is flash ADCs, e.g., flash converters. Flash ADCs may have the advantage of relatively fast conversion speed. However, flash ADCs may suffer from high power consumption due to relatively high input capacitance. As such, flash ADCs may not be suitable for low power and high performance applications. For example, for an I/O application that supports a bandwidth over 10 Gb/s, a flash ADC may consume around 500 mW of power.
A two-stage ADC may trade off reduced power consumption with increased conversion latency. As the name suggests, a two-stage ADC may include a first stage ADC and a second stage ADC. The first stage ADC may coarsely convert the input analog signal into a first digital output signal. A difference between the input analog signal and the first digital output signal may then be generated, which may be referred to as the “residual signal.” The second stage ADC may take the residual signal and convert it into a second digital output signal. The first and the second digital output signals may then be combined to form a single digital output signal, in which the first digital output signal may correspond to the most significant bit(s) (MSB) portion of the combined digital output signal, and the second digital output may correspond to the least significant bit(s) (LSB) portion of the combined digital output signal.
In conventional two-stage ADC design, both the first and the second stage ADCs may be flash ADCs. Between the two stages, a digital-to-analog converter (DAC) may convert the first digital output signal back to an analog signal and a subtractor may subtract the initial input analog signal with this converted analog signal to produce the residual signal. Typically, a closed-loop op-amp may also be required as the core of the switched capacitor system and/or to amplify the residual signal before it can be provided to the second stage ADC. Accordingly, the speed and accuracy of the two-stage ADC may be based on the performance of the closed-loop op-amp and the DAC. However, high performance op-amps that meet the bandwidth, latency and power consumption requirements of high performance I/O applications may be difficult to design due to the low supply voltage and the inherent (intrinsic) gains of MOS transistors, in particular with feature length of 100mn or less.